The present invention pertains to a ferroelectric memory that contains ferroelectric capacitors in a 4-transistor structure SRAM (Static Random-Access Memory).
SRAMs have several advantages. For example, as long as the power source voltage is supplied, the written data do not disappear, and it allows high-speed write and read operations. Consequently, it is widely adopted in main memory, cache memory, etc. of computers that require high-speed data access.
Memory cells of the conventional SRAM include the so-called 6-transistor type made up of 6 transistors, the so-called 4-transistor type made of 4 transistors, etc. All of these types can realize high-speed access, and can hold the stored data with good stability.
In recent years, there has been significant progress in the development of more refined semiconductor manufacturing technology with higher density, and there has also been progress in the development of technology using lower power source voltage for reducing power consumption. However, along with this trend of smaller SRAM memory cells and lower power source voltage, new problems have arisen. In particular, in DSPs (Digital Signal Processors), for SRAMs carried together with other operation circuits or processing circuits on the same chip, that is, the so-called on-chip SRAM, the capacitance keeps rising. As the capacitance increases, the standby current (leakage current) becomes larger, which is undesirable.
In the SRAM memory cell, with a decrease in the power source voltage, the amount of charge that moves due to reading or writing of data decreases. Consequently, the data error rate (soft error rate, referred to as SER hereinafter) rises. In the design and manufacture of SRAMs, the following issues related to scale limitations must be addressed: the scale of the power source voltage, the scale of the charge storage node, and the scale of the memory cell. In addition, the requirement for correctness of the stored data is high. For example, for the instruction code that is stored in DSP program memory and that controls the operation of the processor of DSP, it is believed that even 1-bit data errors cannot be tolerated.
As a method for solving the problem related to increase in SER, one may introduce an error check and correction circuit (hereinafter referred to as an ECC circuit). For example, the vertical/horizontal parity system and Hamming code are effective means to correct single-bit soft data. However, ECC has the disadvantage of increased cost and decreased operating speed due to increase in area for redundancy bit and comparison correcting circuit. Consequently, there is a demand for the development of a method with little influence on the access speed, etc. While ECC is realized on the system level in the case of DRAM, DSP has the system already formed on the chip. Consequently, it is important to realize ECC at least in hardware.
In order to realize ECC, in addition to the conventional memory bit, it is necessary to have memory bits for storing codes for performing error detection and correction, and the number of memory bits inevitably increases. For example, when a vertical/horizontal parity system is used in a DRAM with a volume of 16 Mb, a 33-bit parity code is added for every 256 bits. Also, when a Hamming code system is used in DRAM with a volume of 16 Mb, an 8-bit redundancy code is added for every 128 bits. Usually, an increase in the area of about 20% is inevitable due to the ECC circuit. Also, an increase in the ECC circuit and memory cells leads to an increase in the leakage current of transistors that form inverters and transfer gates inside the memory cell. It is believed that because the standby current for the memory rises, ECC is undesirable from the standpoint of power consumption.
Several methods have been proposed to suppress the transistor leakage current. For example, by controlling the threshold voltage by means of the substrate bias or by lowering the power source voltage in standby by means of plural power source voltages, the leakage current is suppressed. In consideration of the variation in manufacturing transistors having a low threshold voltage, such as a threshold voltage of 0.2 V or lower, it is difficult to suppress the leakage current entirely on the mass production level. Consequently, in many proposed methods, transistors with a high threshold voltage are used in the SRAM portion, and transistors with low threshold voltage are used in the logic portion. That is, a dual-threshold voltage system is used. However, when transistors with different threshold voltages are manufactured, since the number of masks of the manufacturing process is increased and the number of implanting steps for control of threshold voltage is increased, the manufacturing cost is expected to increase, and, when high-threshold-voltage devices are used, the performance of the SRAM may degrade.
As a final method for suppressing the leakage current, one may make use of nonvolatile memories, such as ferroelectric memories, which can hold stored data, even when the power source voltage is stopped. However, at present, most of the efforts related to the development of ferroelectric memories are mainly performed with respect to studies on area, speed, and cost relative to DRAMs. For example, the following structures are often adopted: DRAM memory cell or other 1-capacitor/1-capacitor structure, 1-transistor/2-capacitor structure, and 2-transistor/2-capacitor structure. However, in almost all of the examples, memory cells do not have gain cells. Consequently, the operating speed is lower than that of the conventional SRAM.
The purpose of the present invention is to solve the aforementioned problems of the conventional methods by providing a type of ferroelectric memory characterized by the fact that 4 transistors and 2 ferroelectric capacitors are used to form an SRAM-structure ferroelectric memory cell; as a result, while high-speed access is realized, the SER can be improved, and it is possible to realize lower power consumption by means of lower power source voltage and stopping of the power source voltage in standby state.
In order to realize the aforementioned purpose, the present invention provides a type of ferroelectric memory characterized by the following facts: it has a first ferroelectric capacitor connected between a cell plate and a first node; a second ferroelectric capacitor connected between said cell plate and a second node; a first transistor that is connected between said first node and a reference potential and has its gate connected to said second node; a second transistor that is connected between said second node and the reference potential and has its gate connected to said first node; a third transistor that is connected between said first node and a bit line and has its gate connected to a word line; a fourth transistor that is connected between said second node and a complementary bit line and has its gate connected to said word line; a precharge circuit that precharges said bit line and said complementary bit line to a prescribed potential before the read operation; and a first voltage supply circuit that supplies a reference potential or a prescribed voltage to said cell plate; and, the reference potential is supplied to said cell plate when said first voltage supply circuit is in standby state.
Also, according to the present invention, it is preferred that said prescribed voltage be applied in pulse form to said cell plate when said first voltage supply circuit activates said word line.
Also, according to the present invention, it is preferred that it have a second voltage supply circuit that supplies the reference potential to said bit line and said complementary bit line in standby state.